Effects of Gate Stress and Parasitic Package Inductance on the Reliability of GaN HEMTs

Download or read book Effects of Gate Stress and Parasitic Package Inductance on the Reliability of GaN HEMTs written by Cheikh Abdoulahi Tine and published by . This book was released on 2017 with total page 66 pages. Available in PDF, EPUB and Kindle. Book excerpt: Recent advances in the development of gallium nitride (GaN) high electron mobility transistor (HEMT) have shown promising results in the application of high frequency power conversion techniques. GaN transistors are emerging as a credible alternative to silicon (Si) devices in multiple power conversion applications. This is mainly because the characteristics of GaN offer higher electron mobility, electron velocity, and higher breakdown voltage compared to (Si) devices. In spite of the promising attributes offered by GaN devices, significant technological readiness level challenges remain, in order for the technology to be adopted pervasively into the market. These challenges relate to the reliability of the material both at the device-physics level, and at the circuit-implementation level. This thesis presents detailed studies on some of the circuit-level reliability phenomena affecting GaN technology. These studies will offer a better understanding of the limitations associated with GaN so that the technology's beneficial aspects can be leveraged. The first reliability investigation performed was related to a comparison of two 600 V GaN HEMTs based on the same die, however packaged in two different configurations. In order to characterize the performance of the GaN HEMT, a realistic behavioral simulation model was developed in this thesis. The model takes into consideration both the static and dynamic characteristics of the HEMT including drain current variations with respect to gate voltage and drain voltage, ON resistance, intrinsic capacitances, and reverse recovery current and charge. The model was also integrated with values for the per-terminal parasitic package inductances. These values were obtained through empirical measurement. The modeled transistor was then simulated in a converter to analyze the overall performance of the system. Experimental results verified the results obtained by the model. This study thus presents a framework to project and assess the effect of each parasitic inductance on the performance of next generation GaN devices. In the second reliability study, the effect of gate-stress on the performance of normally-off GaN HEMT devices in a boost converter was investigated. The converter's efficiency, output voltage stability, and gate current were evaluated in order to scrutinize the failure mechanisms of pGaN gated lateral GaN devices under high gate stress. It was observed that the transient overshoot of the gate voltage during turn-on becomes switching frequency-dependent once the device has suffered sufficient degradation, leading to a marked decline in converter performance. This observation has not been reported in the previous literature. This improved understanding may allow mitigation of degradation mechanisms in GaN at the fabrication, packaging, and circuit implementation level. The results of this thesis are beneficial in two ways. First it offers insights into the safe and reliable implementation of GaN devices at the circuits-level, thus obviating the need to trade device performance for device safety. Secondly, the gate-stressing investigation unveils degradation characteristics that are of critical importance to the design and fabrication of next generation GaN devices.